PC/CP120 Digital Electronics Lab Introduction to Quartus II Software Design using QSim for Simulation In this tutorial, we will show you how you capture the schematic design for the automatic door opener circuit using Altera Quartus II software. The Problem We are designing a circuit for an automatic door like those you see at supermarkets.
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The door should open only when a person is detected walking through or when a person presses a switch (such as the wheelchair button) to have the door open. The door should only operate if it has been unlocked. output: f = 1 (Opens Door).
inputs. p = 1 Person Detected. h = 1 Switch Holding the Door Open. c = 1 Door Closed/Locked. Want door to open when. the door is unlocked and person walking through (c=0 and p=1).
the door is unlocked and the switch is set to hold it open (c=0 and h=1) E: Drive or flash drive While working in the lab, you will want to work from either the E: drive on the lab machines or for a flash drive. You can copy your directory to your I: drive at the end when you are done, but there are problems working directly on the I: drive in Quartus II. Be sure to copy your files to the I: drive or a flash drive after you are done, since files on the E: drive will be erased. Each time you create a new project in Quartus II, create a new project directory so that all of the files for each project are in one place and not mixed up with files from other projects. Getting Started with Altera Quartus Launch the Altera Quartus software. You should see a screen such as this: Creating a New project Select the File → New Project Wizard; a window like the following will appear.
To select the working directory use the button to browse and select E: CP120 intro. Name the project DoorOpener. (Note that the next field gets filled in automatically.) Select Finish. Don't uses spaces in file or directory names. Creating a new Schematic design Select File → New - A window as seen in the following picture will open.
Select ' Block Diagram/Schematic File' and press OK. This should open a pane where you will design your circuit. This pane is designated Block1.bdf. Save this graphic design file as DoorOpener in your 'intro' directory.
The file will be given the bdf extension; bdf stands for block design file and contains schematics, symbols or block diagrams. Adding text. Select the A below the arrow to the left of your Block Diagram/Schematic File window (also known as the palette). Select a point near the top left in the window with the left mouse key. Type your name and then hit the Enter key. Type your project name and then hit the Enter key. Type the following equation, f = hc' + pc', and then hit the Enter key.
Hit the Esc (escape) key to end text additions. Adding a Component. Click the library icon. The Symbol dialog box will appear. This window lists the available Altera libraries as seen in this image.
Expand the /altera/quartus12.1/quartus/libraries folder, expand the primitives folder and then expand the logic folder. In the logic folder, select the and2 component by double clicking on it (or by selecting it with a single click, then selecting OK). Click the pointer at the desired location in the Block Diagram/Schematic Editor window to insert the AND symbol into the design file. Repeat these steps to enter an OR ( or2) gate and a NOT ( not) gate.
(If you wanted to add multiple NOT gates, you could select the Repeat-insert mode box.) In the same manner that you placed a gate onto the palette, add three input pins and one output pin from the Symbol libraries. Input pins can be found under primitives pin inputs.
Output pins can be found under primitives pin outputs. Name your input and output pins as you name them in your equation. Double click on the pin name to change its name. Never use spaces in pin names; e.g. 'input 1' is a problem - 'input1' and 'input1' are ok. Rearrange your devices in approximately the placement you would like for the logic diagram you are trying to construct.
You can move a component by selecting it with your mouse, holding down the left button and moving it to another location on the palette. Save your design. It is a good idea to save your design often, just in case something bad happens. Save the bdf file with the same name as the project.
Don't use spaces in any file names. Wiring your circuit Select the orthogonal node tool. Place your pointer on the output of one of the input pins and hold the left mouse button down. You should see a cross-hairs or + appear at the output. Drag your pointer to the input of the AND gate. Every time you release the mouse key, the line (wire) ends. If your wire did not reach the AND gate, you can add to the wire by putting your mouse over an end of the wire and again selecting it with your left mouse button and dragging your mouse to another position.
Don't run wires along the edge of a device. This can cause simulation problems.
Don't leave inputs and outputs right next to the chips. Make sure you can actually see some wire between them, otherwise you may have simulation problems. Note: Make sure you do not make the wire too long. If you drag it too far you will see an x; and this is considered an open connection and your design will not compile. To delete a wire or a portion of a wire, simply click on it (it should change color to indicate selection) and press the delete key. If wires are connected to the component as you are moving it, the wires will drag and stay connected to the component.
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This is referred to as 'rubber banding' and is a feature of all major schematic entry design packages. (You can turn rubberbanding on and off using the rubberbanding tool.
)Add the rest of the wires needed to connect the logic diagram. The window should look something like image below. Save your design. Printing We will not print today. But you will need to know how for your project.
To print, go to File Print. If you want to change what appears on the printout or how it appears, go to File Page Setup change print settings. Before printing, you can view what the print will look like by selecting File Print Preview Choosing a Device The programmable device which we'll use for our design can be chosen now. Select Assignments Device from the pull-down menu. Select MAX7000S from the 'Family' pull-down list. Select the 'Specific device selected' and then choose EPM7064SLC44-10, which is the device we are using in our lab.
If you get a message like this, don't worry; it's fine. Circuit Compilation You will need to compile your design to ensure you do not have any errors in your circuit (e.g. You do not have any open connections, etc.) Click on Processing Start Compilation to start compilation. If you get any error messages, you'll need to fix your circuit before you can simulate it. Common causes of errors If you have one of these issues, you need to fix it. Do you have a project (qpf) open, or just a drawing (bdf)?.
Is your project on the I: drive?. Are your project (qpf) and drawing (bdf) files in different directories?. Are there any spaces in your directory or file names? Circuit Simulation Note: In version 13.0 of Quartus II, QSim can be opened directly from within Quartus II, however it only works with some Cyclone devices.
If you've already chosen a non-Cyclone device, switch to any Cyclone II device to do the simulation. Once you know your logic is correct, you can switch back to your original device. To open QSim, File New New University Waveform File.
Select Edit Insert Insert Node or Bus. Select Node Finder.
Select List. Select the double right arrow to choose all. If you have multiple inputs, you can select a bunch and group them with one counter. Select your input(s), and pick Overwrite Count Value. Select File Save As to give this file a name in your project directory. It will have a VWF extension for Vector Waveform File. In the Main window, select Simulation Options and then select Quartus II Simulator.
Note: If you haven't chosen a Cyclone device, the Quartus II Simulator option will be greyed out. In that case, assign the device to any Cyclone II device and recompile. In the Main window, select Simulation and then select Run Functional Simulation.
( Alternatively, you can you the button on the tool bar.). Now you should see your simulation output with the outputs defined. Note: The file will indicate 'read-only' meaning you can't edit it. You can expand the grouping:.
You can navigate around the timeline, zoom in and out, etc. This part of the output shows that when the inputs are all zero, the output is also zero. This part of the output shows that when c and h are low, and p is high, the output is high.
This part of the output shows that when c and p are low, and h is high, the output is also high. You can repeat this process to check all of the eight possible input combinations. Now if you want, you can go back to the simulation settings and choose Timing instead of Functional to see the effects of propagation delay.
In the Main window, select Simulation and then select Run Timing Simulation. ( Alternatively, you can you the button on the tool bar.) Copy your directory from the E: drive to the I: drive or a flash drive. You'll use this project for future labs.
Demonstrate the circuit to the lab demonstrator. Delete everything from the E: drive so your files don't get used by someone else later.
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TITLE THE DESIGN AND REALISATION OF AN FPGA BASED AUDIO PROCESSOR STUDENT MIKE HUDSON 18022224 PROJECT DR. JOHN HOLDING SUPERVISOR COURSE BENG HON ELECTRICAL AND ELECTRONIC ENGINEERING 9/05/2012 Mike Hudson Preface This report describes project work carried out within the Engineering Programme at Sheffield Hallam University from October 2011 to April 2012. The submission of the report is in accordance with the requirements for the award of the degree of “Bachelor of Electrical and Electronic Engineering with Honours” under the auspices of the University. II Mike Hudson Acknowledgements I would like to thank my supervisor Dr John Holding for his advice and guidance throughout the duration of this project. I would also like to thank every one who has helped me over at the Altera Internet forums. III Mike Hudson Abstract This project report documents the use of a field programmable gate array (FPGA) for real-time processing of audio. The traditional software approach to digital signal processing often introduces an unacceptable delay between the audio input and the audio output (referred to as the total system latency).
This can be problematic for applications that require real-time operation such as live processing of musical instruments. An FPGA design allows the same software routines to be implemented as hardware, therefore eliminating high system latency and potential unreliability. Quartus II v11.0 and SOPC Builder have been used to design and create the VHDL code to be synthesised. The implementation of the VHDL design uses the DE2 development board from Altera which is based around a Cyclone EP2C35 FPGA device having 35000 logic elements. Four audio effects were explored and implemented: echo, flanger, filter and reverb.
External control to the FPGA was implemented using rotary encoders to change various effect parameters, and visual feedback been given through an LCD. The final design utilises a Nois II soft-core processor to form part of the user interface. The results show that the total system latency of the FPGA audio processor was considerably less than a computer software application: less than 1ms compared to 10ms. The initial concept has been proven using a total of 11702 logic elements. There is much scope for development of the final project.
Future work could focus of a more user-friendly system in terms of the user interface and also the creation of more advanced audio effects. IV Mike Hudson Table of contents Preface. II Acknowledgements. III Abstract. IV Table of contents.V Nomenclature and abbreviations.
VIII Table of Figures. IX 1 Introduction. 1 1.1 Digital audio processing. 1 1.2 Project aims and objectives. 2 1.1 Previous works and current products.
3 2 Background and Theory. 5 2.1 Background. 5 2.2 Digital audio theory.
5 2.3 The building blocks of basic audio effects. 7 2.4 Digital filter example. 8 2.5 Conclusion. 8 3 Approach.
10 3.1 General. 10 3.2 Selection of Tools and Software. 10 4 The Altera DE2 development board. 12 4.1 Features.
12 5 Altera Quartus II. 14 5.1 Introduction. 14 5.2 SOPC Builder. 14 6 Interfacing Audio to the audio to the FPGA. 16 6.1 The Wolfson WM8781 audio ADC.
16 6.2 Configuration. 18 6.2.1 Sampling frequency. 20 6.2.2 Register map. 20 V Mike Hudson 6.3 Serial/parallel conversion. 21 6.1 Digital serial data stream. 24 6.2 Summary. 24 7 Building a project library of Quartus block symbols.
25 7.1 Multiply. 25 7.2 Sum.
25 7.3 Mixer. 26 7.4 Small delay-line in hardware. 27 7.5 Summary. 28 8 Implementing a buffer in RAM. 29 8.1 Requirements. 29 8.2 Choice of RAM device.
29 8.3 SDRAM controller Core. 29 8.4 Reading/writing to and from the SDRAM. 30 8.5 RAM state machine. 32 8.6 Implementation of a circular buffer. 34 8.7 Multiple read pointers. 36 8.8 Multiple buffer instances. 36 8.9 Summary.
37 9 Echo effect. 39 9.1 Implementation.
39 10 Audio filter. 41 10.1 State variable filter. 41 10.2 Discussion. 43 11 Flanger effect. 44 12 Reverberation effect. 46 12.1 A basic reverb.
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46 12.2 The all-pass filter. 46 12.2.1 Multiple all-pass filters. 48 12.3 Impulse response test. 48 12.4 Comparison with a commercial software reverb. 51 12.5 Summary. 54 VI Mike Hudson 13 Latency test. 56 13.1 Comparison with computer software.
56 13.2 Summary. 57 14 User Interface. 59 14.1 Considerations. 59 14.2 Quadrature rotary encoder. 60 14.3 Interfacing the controls. 62 14.4 Visual feedback.
62 14.5 Discussion and summary. 64 15 Conclusion. 65 15.1 Further work. 65 16 References. 67 17 Appendices. 69 17.1 Quartus II screenshots.
69 17.2 Project photographs.
Pro Edition 1,2,3 Standard Edition 1,2 Lite Edition 1,4 Paid license required The Intel® Quartus® Prime Pro Edition software supports the advanced features in Intel's next-generation FPGAs and SoCs with the Intel Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 GX device families. Paid license required The Intel Quartus Prime Standard Edition software includes extensive support for earlier device families in addition to the Intel Cyclone 10 LP device family. FREE, no license required The Intel Quartus Prime Lite Edition software supports Intel’s low-cost FPGA device families.
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The Quartus software is a complete CAD system for designing digital circuits. For use in teaching, the FPGA University Program recommends the Quartus Prime Lite Edition software, which does not require a license. The licensed commercial version of the Quartus Prime Standard and Pro Edition software is available for installation in university laboratory facilities. To download the Quartus software, click.
The table below shows the latest version of the Quartus software that supports each of our FPGA boards. The Quartus software comes with a Vector Waveform Editor tool to allow users to draw the test input signals for simulation and select which signal should be shown in the simulation results. The method of running the Waveform Editor tool has varied over the various releases of the Quartus software.
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A brief discription of the Waveform Editor tool with regards to different versions of the Quartus software is given below. For more information, please see the FPGA University Program tutorial 'Introduction to Quartus Simulation'. Starting with Quartus software v13.0, the Waveform Editor tool for performing simulations can be opened from within the Quartus software. This is accomplished by selecting “File - New - University Program VWF”.
Test vectors created with this tool can be used in simulation of your circuits by running the ModelSim-Altera simulation tool. The simulator can be started from within the Waveform Editor, or by using the Altera Nativelink flow. For Quartus software v10.1 through 12.1, the Waveform Editor tool could be used only to enter test inputs and set output signals to view. Running simulations was done using a separate tool, Qsim. For Quartus software v10.1 and 11.0, the QSim tool and Waveform Editor must be installed separately by using the FPGA University Program Installer. Beginning with the Quartus software v11.1, the QSim tool and Waveform Editor are bundled with the Quartus software. The QSim tool can be invoked from a command window by using the command 'quartussh -qsim'.
The quartussh executable is part of the Quartus software. It can be found in the folder where the Quartus software is installed, for example C: altera 12.0 quartus bin. For this example of an installation folder you would type the command C: altera 12.0 quartus bin quartussh -qsim. Note that if you are using the Quartus II Subscription Edition software and you are running a 64 bit operating system, then the executable is found in quartus bin64.
For Quartus software v9.1 and earlier, the Waveform Editor tool was included with the Quartus software and used the internal Quartus simulator. We provide SD card images containing an Ubuntu-based Linux distribution for use with our SoC-based DE-series boards. The Linux distribution can be used for embedded Linux exercises and projects. The (OpenCL™) allows a user to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. Emulate your OpenCL C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, pushing the longer compile time to the end when you are pleased with your kernel code results.
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